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SH7040 Datasheet, PDF (315/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2) | |||
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(I/O pins)
Channel 3:
TIOC3A
TIOC3B
TIOC3C
TIOC3D
Channel 4:
TIOC4A
TIOC4B
TIOC4C
TIOC4D
(Clock input)
Internal clock:
Ï/1
Ï/4
Ï/16
Ï/64
Ï/256
Ï/1024
External clock:
TCLKA
TCLKB
TCLKC
TCLKD
(I/O pins)
Channel 0:
TIOC0A
TIOC0B
TIOC0C
TIOC0D
Channel 1:
TIOC1A
TIOC1B
Channel 2:
TIOC2A
TIOC2B
(Interrupt
request signals)
Channel 3:
TGI3A
TGI3B
TGI3C
TGI3D
TGI3V
Channel 4:
TGI4A
TGI4B
TGI4C
TGI4D
TGI4V
Internal data bus
A/D conversion
start request signal
Figure 12.1 MTU Block Diagram
(Interrupt
request signal)
Channel 0:
TGI0A
TGI0B
TGI0C
TGI0D
TGI0V
Channel 1:
TGI1A
TGI1B
TGI1V
TGI1U
Channel 2:
TGI2A
TGI2B
TGI2V
TGI2U
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