SH7040 Datasheet, PDF (792/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

25.3.2 Control Signal Timing
Table 25.5 Control Signal Timing (Conditions: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%,
AV_CC = V_CC ± 10%, AV_ref = 4.5 V to AV_CC, V_SS = AV_SS = 0 V, Ta = –20 to +75° C)
Item
Symbol
Min
Max Unit Figure
RES rise/fall
RES pulse width
MRES pulse width
t , _RESr t_RESf
—
t _RESW
20
t _MRESW
20
200 ns
—
t _cyc
—
t _cyc
25.4
NMI rise/fall
RES setup time^*
MRES setup time^*
NMI setup time^*
IRQ7–IRQ0 setup time (edge detection)
IRQ7–IRQ0 setup time (level detection)
t , _NMIr t_NMIf
—
t _RESS
35
t _MRESS
35
t _NMIS
35
t _IRQES
35
t _IRQLS
35
200 ns
—
ns
—
ns
—
ns
—
ns
—
ns
25.5
25.4,
25.5
NMI hold time
IRQ7–IRQ0 hold time
IRQOUT output delay time
t _NMIH
t _IRQEH
t _IRQOD
35
—
ns 25.5
35
—
ns
—
35
ns
25.6
Bus request setup time
t _BRQS
35
—
ns 25.7
Bus acknowledge delay time 1
t _BACKD1
—
35
ns
Bus acknowledge delay time 2
t _BACKD2
—
35
ns
Bus three-state delay time
t _BZD
—
35
ns
Note: * The RES, MRES, NMI, BREQ, and IRQ7–IRQ0 signals are asynchronous inputs, but
when thesetup times shown here are provided, the signals are considered to have
produced changes at clock rise (for RES, MRES, BREQ) or clock fall (for NMI and IRQ7–
IRQ0). If the setup times are not provided, recognition is delayed until the next clock rise
or fall.
754