SH7040 Datasheet, PDF (750/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

22.7.4 Erase-Verify Mode (n = 1 for Addresses H'00000–H'1FFFF, n = 2 for Addresses
H'20000–H'3FFFF)
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the erase time, erase mode is exited (the En bit in FLMCRn is released, then
the ESUn bit is released at least 10 µs later), the watchdog timer is released after the elapse of 10
µs or more, and the operating mode is switched to erase-verify mode by setting the EVn bit in
FLMCRn. Before reading in erase-verify mode, a dummy write of H'FF data should be made to
the addresses to be read. The dummy write should be executed after the elapse of 20 µs or more.
When the flash memory is read in this state (verify data is read in 32-bit units), the data at the
latched address is read. Wait at least 2 µs after the dummy write before performing this read
operation. If the read data has been erased (all “1”), a dummy write is performed to the next
address, and erase-verify is performed. If the read data is unerased, set erase mode again and
repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/erase-
verify sequence is not repeated more than 60 times. When verification is completed, exit erase-
verify mode, and wait for at least 5 µs. If erasure has been completed on all the erase blocks after
completing erase-verify operations on all these blocks, release the SWE bit in FLMCR1. If there
are any unerased blocks, set erase mode again, and repeat the erase/erase-verify sequence as
before. However, ensure that the erase/erase-verify sequence is not repeated more than 60 times.
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