SH7040 Datasheet, PDF (116/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 3.2 indicates the setting method for the clock mode.
Table 3.2 Clock Mode Setting
MD3
0
0
1
1
MD2
0
1
0
1
Clock Mode
PLL ON × 1
PLL ON × 2
PLL ON × 4
Reserved (PROM mode only)
3.2 Explanation of Operating Modes
Table 3.3 describes the operating modes.
Table 3.3 Operating Modes
Mode
(MCU) Mode 0
(MCU) Mode 1
(MCU) Mode 2
Mode 3 (single chip
mode)
Mode 4 (PROM mode)
Clock mode
Description
CS0 area becomes an external memory space with 8-bit bus width for
the 112-pin version, and 16-bit for the 144-pin version.
CS0 area becomes an external memory space with 16-bit bus width for
the 112-pin version, and 32-bit for the 144-pin version
The on-chip ROM becomes effective. The bus width for the on-chip ROM
space is 32 bit.
Any port can be used, but external addresses can not be employed.
On-chip ROM can be programmed using a general PROM writer.
The input waveform frequency can be used as is, doubled or quadrupled
as an internal clock in modes 0 to 3.
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