SH7040 Datasheet, PDF (348/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Bit 5—Underflow Flag (TCFU): This status flag indicates the occurrence of a channel 1, 2
TCNT counter underflow.
This bit is reserved in channels 0, 3, and 4. This bit always reads as 0. The write value should
always be 0.
Bit 5: TCFU
0
1
Description
Clear condition: With TCFU=1, a 0 write to TCFU after reading it (initial
value)
Set condition: When the TCNT value underflows (H'0000 → H'FFFF)
• Bit 4—Overflow Flag (TCFV): This status flag indicates the occurrence of a TCNT counter
overflow.
Bit 4: TCFV
Description
0
Clear condition: With TCFV =1, a 0 write to TCFV after reading it^*1
(initial value)
1
Set condition: When the TCNT value overflows (H'FFFF → H'0000)^*2
Notes: *1 For channel 4, this flag is cleared by DTC transfer due to TCFV.
*2 For channel 4, this flag is also set when the TCNT value underflows (H'0001 → H'0000)
in complementary PWM mode.
• Bit 3—Input Capture/Output Compare Flag D (TGFD): This status flag indicates the
occurrence of a channel 0, 3, or 4 TGRD register input capture or compare-match.
This bit is reserved in channels 1 and 2. It always reads as 0. The write value should always be
0.
Bit 3: TGFD
0
1
Description
Clear condition: With TGFD = 1, a 0 write to TGFD following a read
(Cleared by DTC transfer due to TGFD) (initial value)
Set conditions:
• When TGRD is functioning as an output compare register
(TCNT = TGRD)
• When TGRD is functioning as input capture (the TCNT value is sent
to TGRD by the input capture signal)
310