SH7040 Datasheet, PDF (444/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• A mask operation
For A mask, the above operation is modified as follows:
In complementary PWM mode, buffer register compare-match flags can be set only for
compare with three counters (TCNT3, TCNT4, and TCNTS).
Special properties of compare match flag disappear and compare match flags of buffer
registers are set to all set values of buffer registers.
Figure 12.92 shows an example when setting the duty setting register to TGR3B, buffer
register to TGR3D and Buffer register to TGR3A-Td.
TGR3A
TCDR
(TGR3A -Td)
TGR3B
TCNT3
TGR3D
TGR3B,
TGR3D
TDDR
H'0000
TIOC3A
TIOC3B
TIOC3D
TGF3B setting
signal
TGF3D setting
signal
Point a
TCNT4
Point b
Point c
Point d
Set signals are output when:
Point a: TGR3D setting is Td
Point b: TGR3D settings are TGR3A-Td, TGR3A-2Td
Point c: TGR3D settings are Td, 2Td
Point d: TGR3D settings are TGR3A-Td, TGR3A-2Td
Figure. 12.92 Special Properties of Compare Match Flag in Complementary PWM Mode
(for A Mask)
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