SH7040 Datasheet, PDF (700/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

19.6.2 Port E Data Register (PEDR)
PEDR is a 16-bit read/write register that stores data for port E. The bits PE15DR–PE0DR
correspond to the PE15/TIOC4D/DACK1/IRQOUT–PE0/TIOC0A/DREQ0 pins. When the pins
are used as ordinary outputs, they will output whatever value is written in the PEDR; when PEDR
is read, the register value will be read regardless of the pin status. When the pins are used as
ordinary inputs, the pin status rather than the register value is read directly when PEDR is read.
When a value is written to PEDR, that value can be written into PEDR, but it will not affect the
pin status. Table 19.17 shows the read/write operations of the port E data register.
PEDR is initialized by a external power-on reset. However, PEDR is not initialized for a manual
reset, reset by WDT, standby mode, or sleep mode, so the previous data is retained.
Bit: 15
14
13
12
11
10
9
8
PE15DR PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 19.17 Read/Write Operation of the Port E Data Register (PEDR)
PEIOR
0
1
Pin Status
Read
Ordinary input Pin status
Other function Pin status
Ordinary output PEDR value
Other function PEDR value
Write
Can write to PEDR, but it has no effect on pin status
Can write to PEDR, but it has no effect on pin status
Value written is output by pin
Can write to PEDR, but it has no effect on pin status
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