SH7040 Datasheet, PDF (447/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

12.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-
Synchronous PWM Mode
When making a transition from channel 3 or 4 normal operation or PWM mode 1 to reset-
synchronous PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D,
TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-impedance state, followed by the transition to
reset-synchronous PWM mode and operation in that mode, the initial pin output will not be
correct.
When making a transition from normal operation to reset-synchronous PWM mode, write H'11 to
registers TIOR3H, TIOR3L, TIOR4H, and TIOR4L to initialize the output pins to low level
output, then set an initial register value of H'00 before making the mode transition.
When making a transition from PWM mode 1 to reset-synchronous PWM mode, first switch to
normal operation, then initialize the output pins to low level output and set an initial register value
of H'00 before making the transition to reset-synchronous PWM mode.
12.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode
When channels 3 and 4 are in complementary PWM mode or reset-synchronous PWM mode, the
PWM waveform output level is set with the OLSP and OLSN bits in the timer output control
register (TOCR). In the case of complementary PWM mode or reset-synchronous PWM mode,
TIOR should be set to H'00.
12.7.20 Cautions on Using the Chopping Function in Complementary PWM Mode or Reset
Synchronous PWM Mode (A Mask Excluded)
When channels 3 and 4 are in complementary PWM mode or reset-synchronous PWM mode and
using the chopping output function, setting the PWM waveform output level to low active with the
OLSP and OLSN bits in the timer output control register (TOCR) will output an incorrect gate
signal or chopping output.
When channels 3 and 4 are in complementary PWM mode or reset-synchronous PWM mode and
using the chopping output function, the PWM output level should be set to high active.
12.7.21 Cautions on Carrying Out Buffer Operation of Channel 0 in PWM Mode (A Mask
Excluded)
In PWM mode 1, the TGRA and TGRB registers are used in pairs and PWM waveform is output
to the TIOCA pin. In the same manner, the TGRC and TGRD registers are used in pairs and PWM
waveform is output to the TIOCC pin. If either the TGRC or TGRD register is operating as a
buffer register, the TIOCC pin cannot execute default output setting or PWM waveform output
with the I/O control register (TIOR).
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