SH7040 Datasheet, PDF (144/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 6.3 Interrupt Exception Processing Vectors and Priorities (cont)
Interrupt Vector
Interrupt Source
Vector
No.
Vector Table
Address
Offset
MTU3 TGI3A 112
H'000001C0–
H'000001C3
TGI3B 113
H'000001C4–
H'000001C7
TGI3C 114
H'000001C8–
H'000001CB
TGI3D 115
H'000001CC–
H'000001CF
TCI3V 116
H'000001D0–
H'000001D3
MTU4 TGI4A 120
H'000001E0–
H'000001E3
TGI4B 121
H'000001E4–
H'000001E7
TGI4C 122
H'000001E8–
H'000001EB
TGI4D 123
H'000001EC–
H'000001EF
TCI4V 124
H'000001F0–
H'000001F3
Reserved 125
H'000001F4–
H'000001F7
SCI0
ERI0
128
H'00000200–
H'00000203
RXI0
129
H'00000204–
H'00000207
TXI0
130
H'00000208–
H'0000020B
TEI0
131
H'0000020C–
H'0000020F
Interrupt
Priority
(Initial
Value)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
Corre-
sponding
IPR (Bits)
IPRE
(7–4)
Priority
within IPR
Setting Default
Range Priority
High
High
IPRE
(3–0)
IPRF
(15–12)
Low
—
High
IPRF
(11–8)
IPRF
(7–4)
Low
High
Low
High
Low
Low
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