SH7040 Datasheet, PDF (767/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 22.12 Commands of the Programmer Mode
Command Name
Number
of Cycles Mode
First Cycle
Address Data
Second Cycle
Mode Address Data
Memory read mode 1+n
write
X
H'00
read
RA
Dout
Auto-program mode 129
write
X
H'40
write WA
Din
Auto-erase mode
2
write
X
H'20
write X
H'20
Status read mode
2
write
X
H'71
write X
H'71
Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous
128-byte write.
2. In memory read mode, the number of cycles depends on the number of address write
cycles (n).
22.11.3 Memory Read Mode
Table 22.13 AC Characteristics in Transition to Memory Read Mode
(Conditions: V_CC = 5.0 V ±10%, V_SS = 0 V, T_a = 25°C ±5°C)
Item
Command write cycle
CE hold time
CE setup time
Data hold time
Data setup time
Write pulse width
WE rise time
WE fall time
Symbol
t _nxtc
t _ceh
t _ces
t _dh
t _ds
t _wep
t_r
t_f
Min
20
0
0
50
50
70
Max
Unit
Notes
µs
ns
ns
ns
ns
ns
30
ns
30
ns
729