SH7040 Datasheet, PDF (426/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Status Flag Clearing Timing: The status flag is cleared when the CPU reads a 1 status followed
by a 0 write. For DTC/DMA controller activation, clearing can also be done automatically. Figure
12.74 shows the timing for status flag clearing by the CPU. Figure 12.75 shows timing for clearing
due to the DTC/DMA controller.
TSR write cycle
T₁
T₂
φ
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 12.74 Timing of Status Flag Clearing by the CPU
DTC/DMAC
read cycle
T₁
T₂
DTC/DMAC
write cycle
T₁
T₂
φ
Address
Status flag
Source
address
Destination
address
Interrupt
request signal
Figure 12.75 Timing of Status Flag Clearing by DTC/DMAC Activation
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