SH7040 Datasheet, PDF(251/923 Page) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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SH7040 Datasheet, PDF (251/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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Section 11 Direct Memory Access Controller (DMAC)

11.1 Overview

The SH7040 Series includes an on-chip four-channel direct memory access controller (DMAC).

The DMAC can be used in place of the CPU to perform high-speed data transfers among external

devices equipped with DACK (transfer request acknowledge signal), external memories, memory-

mapped external devices, and on-chip peripheral modules (except for the DMAC, DTC, BSC, and

UBC). Using the DMAC reduces the burden on the CPU and increases operating efficiency of the

LSI as a whole.

11.1.1 Features

The DMAC has the following features:

â¢ Four channels

â¢ Four Gbytes of address space in the architecture

â¢ Byte, word, or longword selectable data transfer unit

â¢ 16 Mbytes (16,777,216 transfers, maximum)

â¢ Single or dual address mode. Dual address mode can be direct or indirect address transfer.

ï£§ Single address mode: Either the transfer source or transfer destination (peripheral device) is

accessed by a DACK signal while the other is accessed by address. One transfer unit of

data is transferred in each bus cycle.

ï£§ Dual address mode: Both the transfer source and transfer destination are accessed by

address. Dual address mode can be direct or indirect address transfer.

â¢ Direct access: Values set in a DMAC internal register indicate the accessed address for

both the transfer source and transfer destination. Two bus cycles are required for one

data transfer.

â¢ Indirect access: The value stored at the location pointed to by the address set in the

DMAC internal transfer source register is used as the address. Operation is otherwise

the same as direct access. This function can only be set for channel 3. Four bus cycles

are required for one data transfer.

â¢ Channel function: Transfer modes that can be set are different for each channel. (Dual address

mode indirect access can only be set for channel 1. Only direct access is possible for the other

channels.)

ï£§ Channel 0: Single or dual address mode. External requests are accepted.

ï£§ Channel 1: Single or dual address mode. External requests are accepted.

ï£§ Channel 2: Dual address mode only. Source address reload function operates every fourth

transfer.

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