SH7040 Datasheet, PDF(269/923 Page) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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SH7040 Datasheet, PDF (269/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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transfers are enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon

the input of a transfer request signal.

The transfer request source need not be the data transfer source or transfer destination. However,

when the transfer request is set by RxI (transfer request because SCIâs receive data is full), the

transfer source must be the SCIâs receive data register (RDR). When the transfer request is set by

TxI (transfer request because SCIâs transmit data is empty), the transfer destination must be the

SCIâs transmit data register (TDR). Also, if the transfer request is set to the A/D converter, the

data transfer destination must be the A/D converter register.

Table 11.4 Selecting On-Chip Peripheral Module Request Modes with the RS Bits

DMAC Transfer

RS3 RS2 RS1 RS0 Request Source

DMA Transfer

Destin-

Request Signal Source ation Bus Mode

0 1 1 0 MTU*2

TGI0A

Any*1 Any*1 Burst/cycle steal

0 1 1 1 MTU*2

TGI1A

Any*1 Any*1 Burst/cycle steal

1 0 0 0 MTU*2

TGI2A

Any*1 Any*1 Burst/cycle steal

1 0 0 1 MTU*2

TGI3A

Any*1 Any*1 Burst/cycle steal

1 0 1 0 MTU*2

TGI4A

Any*1 Any*1 Burst/cycle steal

1 0 1 1 A/D

ADI*5

ADDR*4 Any*1 Burst/cycle steal

1 1 0 0 SCI0*3 transmit block TxI0

Any*1 TDR0 Burst/cycle steal

1 1 0 1 SCI0*3 transmit block RxI0

RDR0 Any*1 Burst/cycle steal

1 1 1 0 SCI1*3 transmit block TxI1

Any*1 TDR1 Burst/cycle steal

1 1 1 1 SCI1*3 transmit block RxI1

RDR1 Any*1 Burst/cycle steal

Notes: *1 External memory, memory-mapped external device, on-chip memory, on-chip

peripheral module (excluding DMAC, DTC, BSC, UBC).

*2 MTU: Multifunction timer pulse unit.

*3 SCI0, SCI1: Serial communications interface.

*4 ADDR0, ADDR1: A/D converterâs A/D register.

*5 ADI1 for A mask.

In order to output a transfer request from an on-chip peripheral module, set the relevant interrupt

enable bit for each module, and output an interrupt signal.

When an on-chip peripheral moduleâs interrupt request signal is used as a DMA transfer request

signal, interrupts for the CPU are not generated.

When a DMA transfer is conducted corresponding with one of the transfer request signals in table

11.4, it is automatically discontinued. In cycle steal mode this occurs in the first transfer, and in

burst mode with the last transfer.

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