SH7040 Datasheet, PDF (364/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Counting mode selection
Select counter clock
1
Periodic counter
Select counter
clear source
Select output
compare register
Free-running counter
2
3
Set period
4
Start counting
Periodic counter
5
Start counting
5
Free-running counter
Figure 12.7 Procedure for Selecting the Counting Operation
Free-Running Counter Operation Example: A reset of the MTU timer counters (TCNT) leaves
them all in the free-running mode. When a bit in the TSTR is set to 1, the corresponding timer
counter operates as a free-running counter and begins to increment. When the count overflows
from H'FFFF–H'0000, the TCFV bit in the timer status register (TSR) is set to 1. If the TCIEV bit
in the timer’s corresponding timer interrupt enable register (TIER) is set to 1, the MTU will make
an interrupt request to the interrupt controller. After the TCNT overflows, counting continues from
H'0000. Figure 12.8 shows an example of free-running counter operation.
TCNT value
H'FFFF
H'0000
CST bit
TCFV
326
Figure 12.8 Free-Running Counter Operation
Time