SH7040 Datasheet, PDF (784/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 24.3 Register States in the Standby Mode
Module
Registers Initialized
Registers that
Retain Data
Registers with
Undefined Contents
Interrupt controller
—
(INTC)
All registers
—
User break controller —
(UBC)
All registers
—
Data transfer controller All registers (excluding transfer —
—
(DTC)
data in memory and DTDR)
Cache memory (CAC) —
All registers
—
Bus state controller —
(BSC)
All registers
—
Direct memory access • DMA channel control
—
controller (DMAC)
registers 0–3 (CHCR0–
CHCR3)
• DMA operation register
(DMAOR)
• DMA source
address registers
0–3 (SAR0–
SAR3)
• DMA destination
address registers
0–3 (DAR0–
DAR3)
• DMA transfer
count registers
0–3 (DMATCR0–
DMATCR3)
Multifunction timer
pulse unit (MTU)
Watchdog timer
(WDT)
MTU associated registers
POE associated —
registers
• Bits 7–5 (OVF, WT/IT, TME) • Bits 2–0
—
of the timer control status
(CKS2–CKS0)
register (TCSR)
of the TCSR
• Reset control/status register • Timer counter
(RSTCSR)
(TCNT)
Serial communication • Receive data register (RDR) —
—
interface (SCI)
• Transmit data register (TDR)
• Serial mode register (SMR)
• Serial control register (SCR)
• Serial status register (SSR)
• Bit rate register (BBR)
A/D converter (A/D)
Compare match timer
(CMT)
All registers
All registers
—
—
—
—
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