SH7040 Datasheet, PDF (276/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

1st bus cycle
DMAC
SAR
DAR
Data buffer
Memory
Transfer source
module
Transfer destination
module
The SAR value is taken as the address, and data is read from the transfer source
module and stored temporarily in the DMAC.
2nd bus cycle
DMAC
SAR
DAR
Data buffer
Memory
Transfer source
module
Transfer destination
module
The DAR value is taken as the address, and data stored in the DMAC's data
buffer is written to the transfer destination module.
Figure 11.7 Direct Address Operation during Dual Address Mode
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