SH7040 Datasheet, PDF (590/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Figure 15.7 shows an example of operation in the group-scan mode when AN0–AN2 are selected.
ADF
Conversion standby
ADST
Set to 1 by software
Conver- _Sam-
Channel 0 ^{sion pling}
standby ₁
A/D
conver-
sion 1
Cleared to 0 by software
Sam-
pling
4
A/D
conver-
sion 4
Conver-
sion
stopped
Channel 1
Conversion
standby
Sam-
pling
2
A/D Conver-
conver- sion
sion 2 standby
Sam-
pling
5
A/D
conver-
sion 5
Channel 2
Conversion standby
Sam-
pling
3
A/D Conver-
conver- sion
sion 3 standby
Sam-
pling
6
Channel 3
Conversion standby
ADDRA
Conversion result 1
Conversion result 4
ADDRB
ADDRC
ADDRD
Conversion result 2
Conversion result 5
Conversion result 3
Figure 15.7 A/D Converter Operation Example (Group-Scan Mode)
15.4.5 Buffer Operation
When conversion ends on the relevant channel, the conversion result is stored in the ADDR, and
simultaneously, the previously stored result is transferred to another ADDR. Buffer operation can
be selected from the following:
• AN0 → ADDRA → ADDRB (Two-stage, one-group operation)
• AN0 → ADDRA → ADDRC, AN1 → ADDRB → ADDRD (Two-stage, two-group
operation)
• AN0 → ADDRA → ADDRB → ADDRC → ADDRD (Four-stage, one-group operation)
552