SH7040 Datasheet, PDF (417/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

12.5.2 DTC/DMAC Activation
DTC Activation: The TGR register input capture/compare-match interrupt of any channel can be
used as a source to activate the on-chip data transfer controller (DTC). For details, refer to section
8, Data Transfer Controller (DTC).
The MTU has 17 input capture/compare-match interrupts that can be used as DTC activation
sources, four each for channels 0 and 3, two each for channels 1 and 2, and five for channel 4.
DMAC Activation: The TGRA register input capture/compare-match interrupt of any channel
can be used as a source to activate the on-chip DMAC. For details, refer to section 11, Direct
Memory Access Controller (DMAC).
The MTU has 5 TGRA register input capture/compare-match interrupts, one for any channel, that
can be used as DMAC activation sources.
12.5.3 A/D Converter Activation
The TGRA register input capture/compare-match of any channel can be used to activate the on-
chip A/D converter.
If the TTGE bit of the TIER is already set to 1 when the TGFA flag in the TSR is set to 1 by a
TGRA register input capture/compare-match of any of the channels, an A/D conversion start
request is sent to the A/D converter. If the MTU conversion start trigger is selected at such a time
on the A/D converter side when this happens, the A/D conversion starts.
The MTU has 5 TGRA register input capture/compare-match interrupts, one for each channel, that
can be used as A/D converter activation sources.
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