SH7040 Datasheet, PDF (835/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

CK
A21–A0
RAS
CASxx
(During read)
RDWR
(During read)
D31–D0
(During read)
CASxx
(During write)
RDWR
(During write)
D31–D0
(During write)
WAIT
DACKn
RD
(During read)
WRxx
(During write)
Tp
Tr
Tc1
t_AD
t_AD
Row address
t_ASR
t_{RASD1 tRAH}
t_RP
Tcw1
Tcw2
Column address
t_CASD1
Tcwo
Tc2
t_RASD2
t_CASD2
t_RWD1
t_WDD
t_DACKD1
t_RSD1
t_WSD1
t_CAC
t_AA
t_RAC
t_CASD1
t_DS
t_DH
t_WTS
t_WTH
t_WTS
t_WTH
Note: t_RDH is specified from fastest negate timing of A21–A0, RAS, and CAS.
t_RDS
t_RDH
t_CASD2
t_RWD2
t_WDH
t_DACKD1
t_RSD2
t_WSD2
Figure 26.15 DRAM Cycle (Normal Mode, 2 Waits + Wait due to WAIT Signal)
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