SH7040 Datasheet, PDF (395/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Outline of Complementary PWM Mode Operation: In complementary PWM mode, 6-phase
PWM output is possible. Figure 12.39 illustrates counter operation in complementary PWM
mode, and figure 12.40 shows an example of complementary PWM mode operation.
• Counter operation
In complementary PWM mode, three counters—TCNT3, TCNT4, and TCNTS—perform
up/down-count operations.
TCNT3 is automatically initialized to the value set in TDDR when complementary PWM
mode is selected and the CST bit in TSTR is 0.
When the CST bit is set to 1, TCNT3 counts up to the value set in TGR3A, then switches to
down-counting when it matches TGR3A,. When the TCNT3 value matches TDDR, the counter
switches to up-counting, and the operation is repeated in this way.
TCNT4 is initialized to H'0000.
When the CST bit is set to 1, TCNT4 counts up in synchronization with TCNT3, and switches
to down-counting when it matches TCDR . On reaching H'0000, TCNT4 switches to up-
counting, and the operation is repeated in this way.
TCNTS is a read-only counter. It need not be initialized.
When TCNT3 matches TCDR during TCNT3 and TCNT4 up/down-counting, down-counting
is started, and when TCNTS matches TCDR, the operation switches to up-counting. When
TCNTS matches TGR3A, it is cleared to H'0000.
When TCNT4 matches TDDR during TCNT3 and TCNT4 down-counting, up-counting is
started, and when TCNTS matches TDDR, the operation switches to down-counting. When
TCNTS reaches H'0000, it is set with the value in TGR3A.
TCNTS is compared with the compare register and temporary register in which the PWM duty
is set during the count operation only.
Counter value
TCNT3
TCNT4
TCNTS
TGR3A
TCDR
TDDR
H'0000
TCNT3
TCNT4 _TCNTS
Figure 12.39 Complementary PWM Mode Counter Operation
Time
357