SH7040 Datasheet, PDF(309/923 Page) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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SH7040 Datasheet, PDF (309/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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Table 11.13 Transfer Conditions and Register Set Values for Transfer between External

Memory and SCI1 Sending Side

Transfer Conditions

Transfer source: external memory

Value stored in address H'00400000

Value stored in address H'00450000

Transfer destination: on-chip SCI TDR1

Transfer count: 10 times

Transfer source address: incremented

Transfer destination address: fixed

Transfer request source: SCI1 (TDR1)

Bus mode: cycle steal

Transfer unit: byte

Interrupt request not generated at end of transfer

Channel priority ranking: 0 > 1 > 2 > 3

Register

SAR3

â

â

DAR3

DMATCR3

CHCR3

DMAOR

Value

H'00400000

H'00450000

H'55

H'FFFF81B3

H'0000000A

H'00011E01

H'0001

When indirect address mode is on, the data stored in the address established in SAR is not used as

the transfer source data. In the case of indirect addressing, the value stored in the SAR address is

read, then that value is used as the address and the data read from that address is used as the

transfer source data, then that data is stored in the address designated by the DAR.

In the table 11.13 example, when a transfer request from the TDR1 of SCI1 is generated, a read of

the address located at H'00400000, which is the value set in SAR3, is performed first. The data

H'00450000 is stored at this H'00400000 address, and the DMAC first reads this H'00450000

value. It then uses this read value of H'00450000 as an address and reads the value of H'55 that is

stored in the H'00450000 address. It then writes the value H'55 to the address H'FFFF81B3

designated by DAR3 to complete one indirect address transfer.

With indirect addressing, the first executed data read from the address established in SAR3 always

results in a longword size transfer regardless of the TS0, TS1 bit designations for transfer data

size. However, the transfer source address fixed and increment or decrement designations are as

according to the SM0, SM1 bits. Consequently, despite the fact that the transfer data size

designation is byte in this example, the SAR3 value at the end of one transfer is H'00400004. The

write operation is exactly the same as an ordinary dual address transfer write operation.

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