SH7040 Datasheet, PDF (620/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

16.5 Interrupt and DMA, DTC Transfer Requests
The mid-speed A/D converter generates A/D conversion complete interrupt when completing A/D
conversion.
The ADI interrupt request can be enabled or disabled by the ADIE bit of ADCSR. It is also
possible to activate DMA or DTC transfer by the ADI interrupt request. It is possible to activate
DTC with ADI0 interrupt of A/D0 and activate DMAC with ADI1 interrupt of A/D1. Table 16.5
shows the interrupt factors of the mid-speed A/D converter.
Table 16.5 Mid-speed A/D Converter Interrupt Factors
Mid-speed
A/D converter Interrupt Factor Content
DTC
A/D0
ADI0
Interrupt by conversion complete O
A/D1
ADI1
×
O: activation enabled
×: activation disabled
DMAC
×
O
When accessing the A/D0 register with DTC activated by ADI0 interrupt, the ADF bit of the A/D0
control/status register (ADCSR0) will automatically be cleared to 0. Furthermore, it is possible to
automatically clear the ADF bit of ADCSR1 by register access of A/D1 with activated DMAC of
ADI1 interrupt. For details on the automatic clearing operation of this interrupt factor, see section
8, Data Transfer Controller (DTC).
582