SH7040 Datasheet, PDF (440/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

When setting the buffer operation in the reset synchronous PWM mode, it is not necessary to
set the timer interrupt enable register’s (TIER4) TGIEC and TGIED bits to 0, to prohibit
interrupt output.
Figure 12.88 shows an example of operations for TGR3, TGR4, TIOC3, and TIOC4, with
TMDR3’s BFA and BFB bits set to 1, and TMDR4’s BFA and BFB bits set to 0.
TGR3A
TGR3C
TGR3B,TGR4A
TGR4B
TGR3D,TGR4C
TGR4D
H'0000
Point b
TIOC3A
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
TGF3C
TGF3D
TGF4C
TGF4D
TCNT3
Point a
Not set
Not set
Not set
Not set
Buffer transfer with compare match A3
TGR3A,
TGR3C
TGR3B,TGR3D
TGR4A,TGR4C
TGR4B,TGR4D
Figure 12.88 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode
(for A Mask)
12.7.14 Overflow Flags in Reset Sync PWM Mode
When set to reset sync PWM mode, TCNT3 and TCNT4 start counting when the CST3 bit of
TSTR is set to 1. At this point, TCNT4’s count clock source and count edge obey the TCR3
setting.
In reset sync PWM mode, with cycle register TGR3A’s set value at H'FFFF, take care when
specifying TGR3A compare-match for the counter clear source, since the operation of the
overflow flag (TCFV bit) differs with TSR3 and TSR4.
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