SH7040 Datasheet, PDF (665/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

18.3.10 Port D I/O Register L (PDIORL)
The port D I/O register L (PDIORL) is a 16-bit read/write register that selects input or output for
the least significant sixteen port D pins. Bits PD15IOR–PD0IOR correspond to the PD15/D15 pin
to PD0/D0 pin. PDIORL is enabled when the port D pins function as general input/outputs
(PD15–PD0). For other functions, it is disabled.
For port D pin functions PD15–PD0, a given pin in port D is an output pin if its corresponding
PDIORL bit is set to 1, and an input pin if the bit is cleared to 0.
PDIORL is initialized to H'0000 by external power-on reset; however, it is not initialized for
manual resets, reset by WDT, standby mode, or sleep mode, so the previous data is maintained.
Bit: 15
14
13
12
11
10
9
8
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8
IOR
IOR
IOR
IOR
IOR
IOR
IOR
IOR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
IOR
IOR
IOR
IOR
IOR
IOR
IOR
IOR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
18.3.11 Port D Control Registers H1, H2 (PDCRH1 and PDCRH2)
PDCRH1 and PDCRH2 are 16-bit read/write registers that select the functions of the most
significant sixteen multiplexed pins of port D. PDCRH1 selects the functions of the
PD31/D31/ADTRG–PD24/D24/DREQ0 pins of port D; PDCRH2 selects the functions of the
PD23/D23/IRQ7–PD16/D16/IRQ0 pins of port D. There are instances when these register settings
will be ignored, depending on the operation mode. Refer to table 18.2, Pin Arrangement by Mode,
for details.
The settings for this register are effective only for the 144-pin version. There are no corresponding
pins for this register in the 112-pin and 120-pin versions. However, read/writes are possible.
PDCRH1 and PDCRH2 are both initialized to H'0000 by external power-on reset but are not
initialized for manual resets, reset by WDT, standby mode, or sleep mode, so the previous data is
maintained.
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