SH7040 Datasheet, PDF (260/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Bit 19—Source Address Reload (RO): Selects whether to reload the source address initial
value during channel 2 transfer. This bit is valid only for channel 2. It always reads 0 for
CHCR0, CHCR1, and CHCR3, and cannot be modified.
Bit 19: RO
0
1
Description
Does not reload source address (initial value)
Reloads source address
• Bit 18—Request Check Level (RL): Selects whether to output DRAK notifying external
device of DREQ received, with active high or active low. This bit is valid only for CHCR0 and
CHCR1. It always reads 0 for CHCR2 and CHCR3, and cannot be modified.
Bit 18: RL
0
1
Description
Output DRAK with active high (initial value)
Output DRAK with active low
• Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether to output DACK in
the data write cycle or data read cycle. In single address mode, DACK is always output
irrespective of the setting of this bit. This bit is valid only for CHCR0 and CHCR1. It always
reads as 0 for CHCR2 and CHCR3, and cannot be modified.
Bit 17: AM
0
1
Description
Outputs DACK during read cycle (initial value)
Outputs DACK during write cycle
• Bit 16—Acknowledge Level (AL): Specifies whether to set DACK (acknowledge) signal
output to active high or active low. This bit is valid only with CHCR0 and CHCR1. It always
reads as 0 for CHCR2 and CHCR3, and cannot be modified.
Bit 16: AL
0
1
Description
Active high output (initial value)
Active low output
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