SH7040 Datasheet, PDF(171/923 Page) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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SH7040 Datasheet, PDF (171/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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Section 8 Data Transfer Controller (DTC)

8.1 Overview

The SH7040 Series has an on-chip data transfer controller (DTC), which is activated either by

interrupts or software and can perform data transfers.

8.1.1 Features

â¢ Arbitrary channel number transfer setting possible

ï£§ Transfer information can be established for each interrupt source

ï£§ Transfer information stored in memory

ï£§ Multiple data transfers possible (chain transfers) for one activating source

â¢ Address space: 32-bit addresses can be designated for both transfer source and destination

â¢ Transfer devices

ï£§ Memory: On-chip ROM, on-chip RAM, external ROM, external RAM

ï£§ On-chip peripheral modules (excluding DMAC/DTC)

ï£§ Memory-mapped external devices

â¢ Abundant transfer modes

ï£§ Can select between normal mode/repeat mode/block transfer mode

ï£§ Can select between increment/decrement/fixed for source/destination address

â¢ Transfer units can be set as byte/word/longword

â¢ Interrupts activating the DTC can be requested of the CPU

ï£§ Interrupt requests can be generated to the CPU after completion of a data transfer

ï£§ Interrupt requests generated to the CPU after completion of all designated data transfers

â¢ Transfers can be activated by software

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