SH7040 Datasheet, PDF (283/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

11.3.8 Relationship between Request Modes and Bus Modes by DMA Transfer Category
Table 11.6 shows the relationship between request modes and bus modes by DMA transfer
category.
Table 11.6 Relationship of Request Modes and Bus Modes by DMA Transfer Category
Address
Mode Transfer Category
Request
Mode
Bus^*6 Transfer Usable
Mode Size (Bits) Channels
Single External device with DACK and
external memory
External
B/C 8/16/32 0, 1
External device with DACK and
memory-mapped external device
External
B/C 8/16/32 0, 1
Dual External memory and external memory Any^*1
B/C 8/16/32 0–3^*5
External memory and memory-mapped Any^*1
external device
B/C 8/16/32 0–3^*5
Memory-mapped external device and Any^*1
memory-mapped external device
B/C 8/16/32 0–3^*5
External memory and on-chip memory Any^*1
B/C 8/16/32 0–3^*5
External memory and on-chip
peripheral module
Any^*2
B/C^*3 8/16/32^*4 0–3^*5
Memory-mapped external device and Any^*1
on-chip memory
B/C 8/16/32 0–3^*5
Memory-mapped external device and Any^*2
on-chip peripheral module
B/C^*3 8/16/32^*4 0–3^*5
On-chip memory and on-chip memory Any^*1
B/C 8/16/32 0–3^*5
On-chip memory and on-chip
peripheral module
Any^*2
B/C^*3 8/16/32^*4 0–3^*5
On-chip peripheral module and on-
chip peripheral module
Any^*2
B/C^*3 8/16/32^*4 0–3^*5
Notes: *1 External request, auto-request or on-chip peripheral module request enabled. However,
in the case of on-chip peripheral module request, it is not possible to specify the SCI or
A/D converter for the transfer request source.
*2 External request, auto-request or on-chip peripheral module request possible. However,
if transfer request source is also the SCI or A/D converter (A/D1 for A mask), the
transfer source or transfer destination must be the SCI or A/D converter (A/D1 for A
mask). For A mask, setting A/D0 as the transfer request source is not permitted.
*3 When the transfer request source is the SCI, only cycle steal mode is possible.
*4 Access size permitted by register of on-chip peripheral module that is the transfer
source or transfer destination.
*5 When the transfer request is an external request, channels 0 and 1 only can be used.
*6 B: Burst, C: Cycle steal
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