SH7040 Datasheet, PDF (731/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Bit: 7
6
5
4
3
2
1
0
FLER
— ESU2 PSU2 EV2 PV2
E2
P2
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R/W R/W R/W R/W R/W R/W
• Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation
on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the
error-protection state.
Bit 7: FLER
0
1
Description
Flash memory is operating normally. (Initial value)
Flash memory program/erase protect (error protect) disabled
Indicates error during flash memory program/erase.
Flash memory program/erase protect (error protect) enabled
[Setting condition] See section 22.8.3, Error protection
• Bit 6—Reserved bit: This bit is always read as 0.
• Bit 5—Erase Setup Bit 2 (ESU2): Prepares for a transition to erase mode (applicable
addresses: H'20000–H'3FFFF). Do not set the PSU2, EV2, PV2, E2, or P2 bit at the same time.
Bit 5: ESU2
0
1
Description
Erase setup release (Initial value)
Erase setup
[Setting condition] When FWE=1 and SWE=1
• Bit 4—Program Setup Bit 2 (PSU2): Prepares for a transition to program mode (applicable
addresses: H'20000–H'3FFFF). Do not set the ESU2, EV2, PV2, E2, or P2 bit at the same time.
Bit 4: PSU2
0
1
Description
Program setup release (Initial value)
Program setup
[Setting condition] When FWE=1 and SWE=1
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