SH7040 Datasheet, PDF (275/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

CK
A21–A0
CSn
D15–D0
WRH
WRL
DACK
Address output to external memory space
Data that is output from the external
device with DACK
WR signal to external memory space
DACK signal to external devices with
DACK (active low)
a. External device with DACK to external memory space
CK
A21–A0
CSn
D15–D0
RD
Address output to external memory space
Data that is output from external memory space
RD signal to external memory space
DACK
DACK signal to external device with DACK
(active low)
b. External memory space to external device with DACK
Figure 11.6 Example of DMA Transfer Timing in the Single Address Mode
11.3.6 Dual Address Mode
Dual address mode is used for access of both the transfer source and destination by address.
Transfer source and destination can be accessed either internally or externally. Dual address mode
is subdivided into two other modes: direct address transfer mode and indirect address transfer
mode.
Direct Address Transfer Mode: Data is read from the transfer source during the data read cycle,
and written to the transfer destination during the write cycle, so transfer is conducted in two bus
cycles. At this time, the transfer data is temporarily stored in the DMAC. With the kind of external
memory transfer shown in figure 11.7, data is read from one of the memories by the DMAC
during a read cycle, then written to the other external memory during the subsequent write cycle.
Figure 11.8 shows the timing for this operation.
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