SH7040 Datasheet, PDF (248/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

SH704x
RAS
RDWR
A0
A1
A2–A10
CASHH
CASHL
AD16–AD31
CASH
CASL
AD0–AD15
256k × 16 bits
DRAM
RAS
WE
OE
A0–A8
UCAS
LCAS
I/O0–I/O15
RAS
WE
OE
A0–A8
UCAS
LCAS
I/O0–I/O15
Figure 10.31 32-Bit Data Bus Width DRAM Connection
10.9 On-Chip Peripheral I/O Register Access
On-chip peripheral I/O registers are accessed from the bus state controller, as shown in table 10.6.
Table 10.6 On-Chip Peripheral I/O Register Access
On-chip
Peripheral Module SCI
MTU,
PFC,
POE INTC PORT CMT A/D^* UBC
Connected bus
width
8bit 16bit 16bit 16bit 16bit 16bit 16bit
Access cycle
2cyc 2cyc 2cyc 2cyc 2cyc 2cyc 3cyc
Note: * A/D of A mask products are accessed in 8-bit width, 3 cyc.
WDT
16bit
3cyc
DMAC DTC
16bit 16bit
3cyc 3cyc
CACHE
16bit
3cyc
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