SH7040 Datasheet, PDF (495/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

13.1.4 Register Configuration
Table 13.2 summarizes the three WDT registers. They are used to select the clock, switch the
WDT mode, and control the reset signal.
Table 13.2 WDT Registers
Address
Name
Abbreviation R/W
Initial Value Write^*1
Read^*2
Timer control/status TCSR
register
R/(W)^*3 H'18
H'FFFF8610 H'FFFF8610
Timer counter
TCNT
R/W
H'00
H'FFFF8611
Reset control/status RSTCSR
register
R/(W)^*3 H'1F
H'FFFF8612 H'FFFF8613
Notes: *1 Write by word transfer. It cannot be written in byte or longword.
*2 Read by byte transfer. It cannot be read in word or longword.
*3 Only 0 can be written in bit 7 to clear the flag.
13.2 Register Descriptions
13.2.1 Timer Counter (TCNT)
The TCNT is an 8-bit read/write upcounter. (The TCNT differs from other registers in that it is
more difficult to write to. See section 13.2.4, Register Access, for details.) When the timer enable
bit (TME) in the timer control/status register (TCSR) is set to 1, the watchdog timer counter starts
counting pulses of an internal clock selected by clock select bits 2–0 (CKS2–CKS0) in the TCSR.
When the value of the TCNT overflows (changes from H'FF to H'00), a watchdog timer overflow
signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode selected
in the WT/IT bit of the TCSR.
The TCNT is initialized to H'00 by a power-on reset and when the TME bit is cleared to 0. It is not
initialized in the standby mode. The TCNT is not initialized by a manual reset from an external
source (MRES), but is initialized by a manual reset from the WDT.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
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