SH7040 Datasheet, PDF (175/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

• Bits 11–10—DTC Mode 1, 0 (MD1, MD0): These bits designate the DTC transfer mode.
Bit 11 (MD1)
0
0
1
1
Bit 10 (MD0)
0
1
0
1
Description
Normal mode
Repeat mode
Block transfer mode
Reserved (setting prohibited)
• Bits 9–8—DTC Data Transfer Size 1, 0 (SZ1, SZ0): These bits designate the data size for data
transfers.
Bit 9 (SZ1)
0
0
1
1
Bit 8 (SZ0)
0
1
0
1
Description
Byte (8 bits)
Word (16 bits)
Longword (32 bits)
Reserved (setting prohibited)
• Bit 7—DTC Transfer Mode Select (DTS): When in repeat mode or block transfer mode, this
bit designates whether the source side or destination side will be the repeat area or block area.
Bit 7 (DTS)
0
1
Description
Destination side is the repeat area or block area
Source side is the repeat area or block area
• Bit 6—DTC Chain Enable (CHNE): This bit designates whether to perform continuous DTC
data transfers with the same activating source. Continued transfer information is read after the
16th byte from the start address of the previous transfer information.
Bit 6 (CHNE)
0
1
Description
DTC data transfer end (activation wait state ensues)
DTC data transfer continue (read continue register information, execute
transfer)
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