SH7040 Datasheet, PDF (299/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Burst Mode, Single Address, and Edge Detection: In burst mode with single address and edge
detection, DREQ sampling is conducted only on the first cycle. In figure 11.24, a dummy cycle is
inserted, at the earliest, three cycles after the timing for the first sampling. During this period, data
is undefined, and DACK is not output. Nor is the number of DMAC transfers counted. Thereafter,
DMAC transfer continues until the data transfer count set in the DMATCR has ended. DREQ
sampling is not conducted during this period. Therefore, DRAK is output on the first cycle only.
When DMAC transfer is resumed after being halted by a NMI or address error, be sure to reinput
an edge request. DRAK is output once, and the remaining transfer restarts after output of one
dummy cycle.
The DACK output period in burst mode is the same as in cycle steal mode.
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