SH7040 Datasheet, PDF (9/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Section
12.9.2 Block
Diagram
Figure 12.125 POE
Block Diagram
Page
444
Description
Note added
TIOC3B^*
TIOC3D^*
TIOC4A^*
TIOC4C^*
TIOC4B^*
TIOC4D^*
12.11.5 Usage
453
Notes
14.2.8 Bit Rate
491
Register (BRR)
Table 14.3 Bit Rates
and BRR Settings in
Asynchronous Mode
(cont)
Table 14.4 Bit Rates 495
and BRR Settings in
Clocked
Synchronous Mode
(cont)
14.3.4 Clock
529
Synchronous
Operation
Figure 14.22
Example of SCI
Receive Operation
Note: * Includes multiplexed pins.
Section added
Table amended
Bit Rate
(Bits/s)
110
150
300
600
1200
2400
4800
9600
14400
19200
28800
31250
38400
27.0336
n N Error (%)
3 119 0.00
3 87 0.00
2 175 0.00
1 87 0.00
1 175 0.00
1 87 0.00
0 175 0.00
0 87 0.00
0 58 –0.56
0 43 0.00
0 28 1.15
0 26 0.12
0 21 0.00
Table amended
3.5M
5M
7M
—
—
0
0^*
Figure amended
Bit 7 Bit 0
—
—
—
—
—
—
0
1
—
—
0
0^*
RxI request