SH7040 Datasheet, PDF(233/923 Page) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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SH7040 Datasheet, PDF (233/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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10.4.4 Burst Operation

High-Speed Page Mode: When the burst enable bit (BE) of the DCR is set, burst accesses can be

performed using high speed page mode. The timing is shown in figure 10.12. Wait cycles can be

inserted during burst accesses by using the DCR.

Tp

Tr

Tc1

Tc2

Tc1

Tc2

CK

Address

Write

Data

RAS

CASx

RDWR

Row

Column

Column

Read

Data

RAS

CASx

RDWR

Figure 10.12 DRAM Bus Cycle (High-Speed Page Mode)

RAS Down Mode: There are some instances where even if burst operation is selected, continuous

accesses to DRAM will not occur, but another space will be accessed instead part way through the

access. In such cases, if the RAS signal is maintained at low level during the time the other space

is accessed, it is possible to continue burst operation at the time the next DRAM same row address

is accessed. This is called RAS down mode.

To use RAS down mode, set both the BE and RASD bits of the DCR to 1.

Figures 10.13 and 10.14 show operation in RAS up and down modes.

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