SH7040 Datasheet, PDF (270/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

11.3.3 Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it selects a
channel according to a predetermined priority order, either in a fixed mode or in round robin
mode. These modes are selected by priority bits PR1 and PR0 in the DMA operation register
(DMAOR).
Fixed Mode: In these modes, the priority levels among the channels remain fixed.
The following priority orders are available for fixed mode:
• CH0 > CH1 > CH2 > CH3
• CH0 > CH2 > CH3 > CH1
• CH2 > CH0 > CH1 > CH3
These are selected by settings of the PR1 and PR0 bits of the DMA operation register (DMAOR).
Round Robin Mode: In round robin mode, each time the transfer of one transfer unit (byte, word
or long word) ends on a given channel, that channel receives the lowest priority level (figure 11.3).
The priority level in round robin mode immediately after a reset is CH0 > CH1 > CH2 > CH3.
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