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| SH7040 Datasheet, PDF (834/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2) | |||
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CK
A21âA0
RAS
CASxx
(During read)
RDWR
(During read)
D31âD0
(During read)
CASxx
(During write)
RDWR
(During write)
D31âD0
(During write)
DACKn
RD
(During read)
WRxx
(During write)
Tp
Tpw
Tr
Trw
Tc1
tAD
tAD
Row address
tASR
tRASD1
tRAH
tRP
Tcw1
Tcw2
Tc2
Column address
tCASD1
tRASD2
tCASD2
tRAC
tCAC
tAA
tCASD1
tRWD1
tWDD
tDS
tDACKD1
tRSD1
tWSD1
tRDS
tRDH
tCASD2
tRWD2
tDH
tWDH
tDACKD1
tRSD2
tWSD2
Note: tRDH is specified from fastest negate timing of A21âA0, RAS, and CAS.
Figure 26.13 DRAM Cycle (Normal Mode, 2 Waits, TPC = 1, RCD = 1)
CK
A21âA0
RAS
CASxx
(During read)
RDWR
(During read)
D31âD0
(During read)
CASxx
(During write)
RDWR
(During write)
D31âD0
(During write)
DACKn
RD
(During read)
WRxx
(During write)
Tp
Tpw
Tr
Trw
Tc1
Tcw1
Tcw2
Tcw3
Tc2
tAD
tAD
Row address
tRASD1
tASR
tRAH
tRP
Column address
tCASD1
tRASD2
tCASD2
tCAC
tAA
tRAC
tCASD1
tRWD1
tDS
tWDD
tDACKD1
tRSD1
tWSD1
tRDS
tRDH
tCASD2
tRWD2
tDH
tWDH
tDACKD1
tRSD2
tWSD2
Note: tRDH is specified from fastest negate timing of A21âA0, RAS, and CAS.
Figure 26.14 DRAM Cycle (Normal Mode, 3 Waits, TPC = 1, RCD = 1)
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