SH7040 Datasheet, PDF(373/923 Page) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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SH7040 Datasheet, PDF (373/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

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TCNT value

TGR0B

TGR0A

H'0000

H'0200

H'0450

TGR0C H'0200

Transfer

TGR0A

H'0200

H'0450

H'0520

H'0450

H'0520

Time

TIOC0A

Figure 12.20 Buffer Operation Example (Output Compare Register)

Buffer Operation Examplesâwhen TGR Is an Input Capture Register: Figure 12.21 shows

an example of TGRA set as an input capture register with the TGRA and TGRB registers set for

buffer operation.

The TCNT counter is cleared by a TGRA register input capture, and the TIOCA pin input capture

input edge is selected as both rising and falling edge. Because buffer mode is selected, an input

capture A causes the TCNT counter value to be stored in the TGRA register, and the value that

was stored in the TGRA up until that time is simultaneously transferred to the TGRC register.

TCNT value

H'0F07

H'09FB

H'0532

H'0000

TIOCA

Time

TGRA

H'0532

H'0F07

H'09FB

TGRC

H'0532

H'0F07

Figure 12.21 Buffer Operation Example (Input Capture Register)

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