SH7040 Datasheet, PDF (225/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

When the wait is specified by software using WCR, the wait input WAIT signal from outside is
sampled. Figure 10.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock
rise one cycle before the clock rise when T_w state shifts to T₂ state.
T₁
T_W
T_W
T_W0
T₂
CK
Address
CSn
Read
RD
Data
Write
WRx
Data
WAIT
Figure 10.5 Wait State Timing of Ordinary Space Access (Wait States from Software Wait
2 State + WAIT Signal)
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