SH7040 Datasheet, PDF (24/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

4.2.2 External Clock Input Method ............................................................................... 82
4.3 Prescaler............................................................................................................................. 83
4.4 Oscillator Halt Function..................................................................................................... 83
4.5 Usage Notes ....................................................................................................................... 83
4.5.1 Oscillator Usage Notes ......................................................................................... 83
4.5.2 Notes on Board Design......................................................................................... 84
4.5.3 Spread Spectrum Clock Generator Usage Notes .................................................. 85
Section 5 Exception Processing..................................................................................... 87
5.1 Overview............................................................................................................................ 87
5.1.1 Types of Exception Processing and Priority......................................................... 87
5.1.2 Exception Processing Operations ......................................................................... 88
5.1.3 Exception Processing Vector Table...................................................................... 89
5.2 Resets................................................................................................................................. 90
5.2.1 Power-On Reset .................................................................................................... 91
5.2.2 Manual Reset ........................................................................................................ 91
5.3 Address Errors ................................................................................................................... 92
5.3.1 Address Error Exception Processing .................................................................... 93
5.4 Interrupts ............................................................................................................................ 93
5.4.1 Interrupt Priority Level......................................................................................... 94
5.4.2 Interrupt Exception Processing............................................................................. 94
5.5 Exceptions Triggered by Instructions ................................................................................ 94
5.5.1 Trap Instructions................................................................................................... 95
5.5.2 Illegal Slot Instructions......................................................................................... 95
5.5.3 General Illegal Instructions................................................................................... 96
5.6 When Exception Sources Are Not Accepted..................................................................... 96
5.6.1 Immediately after a Delayed Branch Instruction.................................................. 96
5.6.2 Immediately after an Interrupt-Disabled Instruction ............................................ 96
5.7 Stack Status after Exception Processing Ends................................................................... 97
5.8 Notes on Use ...................................................................................................................... 98
5.8.1 Value of Stack Pointer (SP).................................................................................. 98
5.8.2 Value of Vector Base Register (VBR) ................................................................. 98
5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing ...... 98
Section 6 Interrupt Controller (INTC)......................................................................... 99
6.1 Overview............................................................................................................................ 99
6.1.1 Features................................................................................................................. 99
6.1.2 Block Diagram...................................................................................................... 99
6.1.3 Pin Configuration ................................................................................................. 101
6.1.4 Register Configuration ......................................................................................... 101
6.2 Interrupt Sources................................................................................................................ 102
6.2.1 NMI Interrupts ...................................................................................................... 102
6.2.2 User Break Interrupt ............................................................................................. 102
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