SH7040 Datasheet, PDF (88/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 2.3 Delayed Branch Instructions
SH7040 Series CPU
BRA
TRGET
ADD
R1,R0
Description
Executes an ADD before
branching to TRGET
Example of Conventional CPU
ADD.W R1,R0
BRA
TRGET
Multiplication/Accumulation Operation: 16-bit × 16-bit → 32-bit multiplication operations are
executed in one to two cycles. 16-bit × 16-bit + 64-bit → 64-bit multiplication/accumulation
operations are executed in two to three cycles. 32-bit × 32-bit → 64-bit and 32-bit × 32-bit + 64-
bit → 64-bit multiplication/accumulation operations are executed in two to four cycles.
T Bit: The T bit in the status register changes according to the result of the comparison, and in
turn is the condition (true/false) that determines if the program will branch. The number of
instructions that change the T bit is kept to a minimum to improve the processing speed (table
2.4).
Table 2.4 T Bit
SH7040 Series CPU
CMP/GE R1,R0
BT
TRGET0
BF
TRGET1
ADD
CMP/EQ
BT
#1,R0
#0,R0
TRGET
Description
Example of Conventional CPU
T bit is set when R0 ≥ R1. The
program branches to TRGET0
when R0 ≥ R1 and to TRGET1
when R0 < R1.
CMP.W
BGE
BLT
R1,R0
TRGET0
TRGET1
T bit is not changed by ADD. T bit is SUB.W #1,R0
set when R0 = 0. The program
branches if R0 = 0.
BEQ TRGET
Immediate Data: Byte (8-bit) immediate data resides in instruction code. Word or longword
immediate data is not input via instruction codes but is stored in a memory table. An immediate
data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode
with displacement (table 2.5).
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