SH7040 Datasheet, PDF (378/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PWM Mode Operation Examples—PWM Mode 2 (Figure 12.26): Channels 0 and 1 are set for
synchronous operation, TGR1B register compare-match is used as a TCNT counter clear source,
the other TGR register initial output value is 0 and output compare output value is 1, and a 5-phase
PWM waveform is output. In this example, the value established in the TGR1B register becomes
the period and the value established in the other TGR register becomes the duty cycle.
TCNT value
TGR1B
TGR1A
TGR0D
TGR0C
TGR0B
TGR0A
H'0000
TIOC0A
Counter cleared on TGR1B compare match
Time
TIOC0B
TIOC0C
TIOC0D
TIOC1A
Figure 12.26 PWM Mode Operation Example (Mode 2)
0% Duty Cycle: Figure 12.27 shows an example of a 0% duty cycle PWM waveform output in
PWM mode.
TCNT value
TGRB rewrite
TGRA
TGRB
TIOCA
TGRB rewrite
0% duty cycle
TGRB rewrite
Time
Figure 12.27 PWM Mode Operation Example (0% Duty Cycle)
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