SH7040 Datasheet, PDF (189/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 8.5 Block Transfer Mode Register Functions
Register
DTMR
DTCRA
DTCRB
DTSAR
DTDAR
Function
Operation mode
control
Transfer count
Block length
Transfer source
address
Transfer destination
address
Values Written Back upon a
Transfer Information Write
DTMR
DTCRA – 1
(Not written back)
(DTS = 0) Increment/ decrement/ fixed
(DTS = 1) DTSAR initial value
(DTS = 0) DTDAR initial value
(DTS = 1) Increment/ decrement/ fixed
8.3.8 Operation Timing
Figure 8.6 shows a DTC operation timing example.
φ
Activating
source
DTC
request
Address
Vector
read
Transfer
information
read
RW
Data
transfer
Transfer
information
write
Figure 8.6 DTC Operation Timing Example (Normal Mode)
When register information is located in on-chip RAM, each mode requires 4 cycles for transfer
information reads, and 3 cycles for writes.
8.3.9 DTC Execution State Counts
Table 8.6 shows the execution state for one DTC data transfer. Furthermore, table 8.7 shows the
state counts needed for execution state.
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