SH7040 Datasheet, PDF (174/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Bit: 15
14
13
12
11
10
9
8
SM1 SM0 DM1 DM0 MD1 MD0 SZ1
SZ0
Initial value: *
*
*
*
*
*
*
*
R/W: —
—
—
—
—
—
—
—
Bit: 7
6
5
4
3
2
1
0
Bit name: DTS CHNE DISEL NMIM —
—
—
—
Initial value: *
*
*
*
*
*
*
*
R/W: —
—
—
—
—
—
—
—
Note: * Initial value undefined.
• Bits 15–14—Source Address Mode 1, 0 (SM1, SM0): These bits designate whether to hold,
increment, or decrement the DTSAR after a data transfer.
Bit 15 (SM1)
0
1
1
Bit 14 (SM0)
—
0
1
Description
DTSAR remains fixed
DTSAR is incremented after transfer
(+1 for byte unit transfer, +2 for word, +4 for longword)
DTSAR is decremented after transfer
(–1 for byte unit transfer, –2 for word, –4 for longword)
• Bits 13–12—Destination Address Mode 1, 0 (DM1, DM0): These bits designate whether to
hold, increment or decrement the DTDAR after a data transfer.
Bit 13 (DM1)
0
1
1
Bit 12 (DM0)
—
0
1
Description
DTDAR remains fixed
DTDAR is incremented after transfer
(+1 for byte unit transfer, +2 for word, +4 for longword)
DTDAR is decremented after transfer
(–1 for byte unit transfer, –2 for word, –4 for longword)
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