SH7040 Datasheet, PDF (356/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Figure 12.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1,
OLSP = 1.
TCNT3 and
TCNT4 values
TGR3A
TGR4A
TCNT4
TCNT3
TDDR
H'0000
Positive
phase output
Initial
output
Compare match
output (up count)
Active level
Compare match
output (down count)
Reverse
phase output
Initial
output
Active
level
Compare match
output (up count)
Compare match
output (down count)
Active level
Figure 12.2 Complementary PWM Mode Output Level Example
Time
12.2.12 Timer Gate Control Register (TGCR)
The timer gate control register (TGCR) is an 8-bit read/write register that controls the waveform
output necessary for brushless DC motor control in complementary PWM mode/reset-
synchronized PWM mode. The TGCR is initialized to H'80 by a power-on reset or in the standby
mode. Manual reset does not initialize TGCR. These register settings are ineffective for anything
other than complementary PWM mode/reset-synchronized PWM mode.
Bit: 7
—
Initial value: 1
R/W: R
6
5
4
3
2
1
0
BDC
N
P
FB
WF
VF
UF
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W
• Bit 7—Reserved: This bit always reads as 1. The write value should always be 1.
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