SH7040 Datasheet, PDF (17/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Section
Page
26.3.3 Bus Timing ⁷⁹⁶
Figure 26.13 DRAM
Cycle (Normal Mode,
2 Waits, TPC = 1,
RCD = 1)
Description
Figure amended
Tcw1
Tcw2
Column address
t_CASD1
t_RAC
t_CAC
t_AA
t_CASD1
Figure 26.14 DRAM ⁷⁹⁶
Cycle (Normal Mode,
3 Waits, TPC = 1,
RCD = 1)
Figure amended
Tcw1
Tcw2
Column address
t_CASD1
t_CAC
t_AA
t_RAC
t_CASD1
26.3.5 Multifunction 802
Timer Pulse Unit
Timing
Figure 26.23 MTU
I/O Timing
Figure amended
CK
Output
compare output
t_TOCD
26.3.11
810
Measurement
Conditions for AC
Characteristics
Figure 26.33 Output
Load Circuit
Title amended
Output Load Circuit