SH7040 Datasheet, PDF (326/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

12.2.2 Timer Mode Register (TMDR)
The TMDR is an 8-bit read/write register that sets the operating mode for each channel. The MTU
has five TMDR registers, one for each channel. TMDR is initialized to H'C0 by a power-on reset
or the standby mode. Manual reset does not initialize TMDR.
Channels 0, 3, 4: TMDR0, TMDR3, TMDR4:
Bit: 7
—
Initial value: 1
R/W: R
6
5
4
3
2
1
0
—
BFB BFA MD3 MD2 MD1 MD0
1
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W
Channels 1, 2: TMDR1, TMDR2:
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
MD3 MD2 MD1 MD0
Initial value: 1
1
0
0
0
0
0
0
R/W: R
R
R
R
R/W R/W R/W R/W
• Bits 7, 6—Reserved: These bits are reserved. They always read as 1, and cannot be modified.
• Bit 5—Buffer Operation B (BFB): Designates whether to use the TGRB register for normal
operation, or buffer operation in combination with the TGRD register. When using TGRD as a
buffer register, no TGRD register input capture/output compares are generated.
This bit is reserved in channels 1 and 2, which have no TGRD registers. It is always read as 0,
and cannot be modified.
Bit 5: BFB
0
1
Description
TGRB operates normally (initial value)
TGRB and TGRD buffer operation
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