SH7040 Datasheet, PDF (509/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

14.1.3 Pin Configuration
Table 14.1 summarizes the SCI pins by channel.
Table 14.1 SCI Pins
Channel
0
1
Pin Name
Serial clock pin
Receive data pin
Transmit data pin
Serial clock pin
Receive data pin
Transmit data pin
Abbreviation Input/Output
SCK0
Input/output
RxD0
Input
TxD0
Output
SCK1
Input/output
RxD1
Input
TxD1
Output
Function
SCI0 clock input/output
SCI0 receive data input
SCI0 transmit data output
SCI1 clock input/output
SCI1 receive data input
SCI1 transmit data output
14.1.4 Register Configuration
Table 14.2 summarizes the SCI internal registers. These registers select the communication mode
(asynchronous or clock synchronous), specify the data format and bit rate, and control the
transmitter and receiver sections.
Table 14.2 Registers
Channel
Name
Abbreviation R/W
Initial
Value
0
Serial mode register SMR0
R/W H'00
Bit rate register
BRR0
R/W H'FF
Serial control register SCR0
R/W H'00
Transmit data register TDR0
R/W H'FF
Serial status register SSR0
R/(W)^*1 H'84
Receive data register RDR0
R
H'00
1
Serial mode register SMR1
R/W H'00
Bit rate register
BRR1
R/W H'FF
Serial control register SCR1
R/W H'00
Transmit data register TDR1
R/W H'FF
Serial status register SSR1
R/(W)^*1 H'84
Receive data register RDR1
R
H'00
Notes: *1 The only value that can be written is a 0 to clear the flags.
*2 Do not access empty addresses.
Access
Address^*2 Size
H'FFFF81A0 8, 16
H'FFFF81A1 8, 16
H'FFFF81A2 8, 16
H'FFFF81A3 8, 16
H'FFFF81A4 8, 16
H'FFFF81A5 8, 16
H'FFFF81B0 8, 16
H'FFFF81B1 8, 16
H'FFFF81B2 8, 16
H'FFFF81B3 8, 16
H'FFFF81B4 8, 16
H'FFFF81B5 8, 16
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