SH7040 Datasheet, PDF (320/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

Table 12.3 Register Configuration (cont)
Chan-
nel Name
Abbrevi-
ation R/W
Initial
Value
Address
Access Size
(Bits) ^*1
4 (cont) Timer counter 4
TCNT4 R/W^*3 H'0000 H'FFFF8212 16, 32
General register 4A
TGR4A R/W^*3 H'FFFF H'FFFF821C
General register 4B
TGR4B R/W^*3 H'FFFF H'FFFF821E
General register 4C
TGR4C R/W H'FFFF H'FFFF8228 16, 32
General register 4D
TGR4D R/W H'FFFF H'FFFF822A
3 and 4 Timer output master enable TOER R/W^*3 H'C0
register
H'FFFF820A 8, 16, 32
Timer output control register TOCR R/W^*3 H'00
H'FFFF820B
Timer gate control register TGCR R/W^*3 H'80
H'FFFF820D
Timer cycle data register TCDR R/W^*3 H'FFFF H'FFFF8214 16, 32
Timer dead time data
register
TDDR R/W^*3 H'FFFF H'FFFF8216
Timer subcounter
TCNTS R
H'0000 H'FFFF8220 16, 32
Timer cycle buffer register TCBR R/W H'FFFF H'FFFF8222
Notes: *1 16-bit registers (TCNT, TGR) cannot be read or written in 8-bit units.
*2 Write 0 to clear flags.
*3 If the MTURWE bit of bus control register 1 (BCR) in the bus state controller (BSC) is 0
cleared, access becomes impossible (undefined read/write disabled).
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