SH7040 Datasheet, PDF (94/923 Pages) Renesas Technology Corp – Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

2.3.3 Instruction Format
Table 2.9 lists the instruction formats for the source operand and the destination operand. The
meaning of the operand depends on the instruction code. The symbols are used as follows:
• xxxx: Instruction code
• mmmm: Source register
• nnnn: Destination register
• iiii: Immediate data
• dddd: Displacement
Table 2.9 Instruction Formats
Instruction Formats
0 format
15
xxxx xxxx xxxx
0
xxxx
n format
15
0
xxxx nnnn xxxx xxxx
m format
15
0
xxxx mmmm xxxx xxxx
Source
Operand
—
Destination
Operand
—
Example
NOP
—
nnnn: Direct
MOVT Rn
register
Control register
or system
register
nnnn: Direct
register
STS MACH,Rn
Control register
or system
register
nnnn: Indirect pre- STC.L SR,@-Rn
decrement register
mmmm: Direct
register
Control register or LDC
system register
Rm,SR
mmmm: Indirect
post-increment
register
Control register or LDC.L @Rm+,SR
system register
mmmm: Direct —
register
JMP @Rm
mmmm: PC
—
relative using Rm
BRAF Rm
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